(1) Field of the Invention
The present invention relates to an operational amplifier, and more particularly to a balanced type operational amplifier.
(2) Description of the Related Art
In a conventional operational amplifier to which the present invention relates, there have been known some circuits for stabilizing an output operation point.
A first example of such circuits is shown in FIG. 1. The circuit is disclosed in IEEE, ISSCC, 1983, pages 246, 247 and 314, entitled "High-Frequency CMOS Switched Capacitor Filters for Communication Applications" by Tat C. Choi et al. In summary, in a single-stage folded cascade type operational amplifier, an N-channel transistor pair 101 which has gates connected to a positive and a negative output terminal of the amplifier, respectively, and which operates in triode region is connected between a constant-current load 102 and a power supply source VS in series. In this operational amplifier, when the common-mode output voltage becomes high, the triode region device of the N-channel transistor pair 101 functions to decrease its resistance value so that negative feedback effect is applied to the operational amplifier thereby lowering the common-mode output voltage.
A second example of such circuits is shown in FIGS. 2A and 2B. The circuit is disclosed in IEEE, JOURNAL OF SOLID-STATE CIRCUITS, Vol. SC-17, No. 6, December 1982, pages 1014-1023, entitled "A Family of Differential NMOS Analog Circuits for a PCM Codec Filter Chip" by Daniel Senderowics et al. In summary, as shown in FIG. 2A, switches driven by clock signals externally applied in combination with the capacitors C1 produce a feedback voltage by adding to a reference voltage R a difference between an average voltage of the actual positive/negative outputs OP, ON from the operational amplifier 201 and an operation point voltage C expected in the same operational amplifier 201 and, then, the feedback voltage thus produced is negatively fedback to the operational amplifier 201 through a feedback path F. FIG. 2B shows a detailed circuit diagram of the operational amplifier 201 in which two differential amplifiers, namely, M1, M2 and M7, M8, with their respective active loads M3, M4 and M9, M10 are provided. The current-source transistor M5 is driven to obtain a local common-mode feedback for the first stage differential amplifier (M1, M2). The above mentioned feedback voltage is applied to a gate of the current-source transistor M6 through the feedback path F so that the operating current of this transistor M6 is controlled to be increased or decreased, thereby stabilizing the output voltage of the operational amplifier 201.
A third example of such circuits is shown in FIG. 3. The circuit is disclosed in IEEE, JOURNAL OF SOLID-STATE CIRCUITS, Vol. SC-19, No. 6, December 1984, pages 912-918, entitled "Power-Supply Rejection in Differential Switched-Capacitor Filters" by Alejandro Dela Plaza et al. In summary, as shown in FIG. 3, the circuit is based on the utilization of the effect that the operating center voltage VC of the operational amplifier can be derived as a voltage developed at an intermediate node between resistors R3 having the same resistance value, connected in series between the positive and negative output terminals of the operational amplifier. The operating center voltage VC is inputted to one input terminal of a differential amplifier 31 and the operating voltage C inherently expected in the operational amplifier is inputted to the other input terminal thereof. The feedback signal FB thus obtained is negatively fedback to the operational amplifier such as shown in FIG. 2B through the feedback path F.
The above conventional circuits for stabilizing the output voltage of the operational amplifier have the following drawbacks.
In the first example of circuit shown in FIG. 1, since the comparison between the actual center voltage of the positive/negative outputs of the operational amplifier and the expected operating center voltage therefor is not conducted precisely, the above actual center voltage does not necessarily correspond to the above expected voltage due to such variations as those in the reference voltages or in the characteristics of the transistors concerned where the circuit is integrated, even though it satisfies the operation range or margin of the amplifier.
In the second example of circuit shown in FIGS. 2A and 2B, since the circuit employs the switching circuits driven by the clock signals, the circuit necessarily requires the provision of a filter for eliminating the feed-through noise that may be caused by the clock signals when the positions of the switching circuits are changed to the side of the feedback path and to the side of the reference voltage source. This is a drawback in the second example of circuit.
In the third example of circuit shown in FIG. 3, since the two resistors R3 from which the operating center voltage of the operational amplifier is derived at their common connection node stand as loads for the operational amplifier, the gain of the operational amplifier is distinctly lowered where the resistance value of the resistors is small. For this reason, the circuit of this third example has a defect in that it necessitates either the high transconductance of the output-stage transistors accompanying an increase of the necessary chip area and a large power consumption or the high resistance value of the resistors accompanying an increase of the necessary chip area and a degradation of the common-mode rejection ration caused by the variations in the resistance value.